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9Nov/18

Toshiba Memory Co., Ltd. successfully developed high-speed, energy-efficient algorithms and hardware architecture for deep learning processors

TOKYO--(BUSINESS WIRE)--Toshiba Memory Corporation, the global leader in memory solutions, today announced the successful development of high-speed, energy-efficient algorithms and hardware architecture for deep learning, reducing recognition accuracy The extent of the decline. The new processor for deep learning on FPGA[1] is four times more energy efficient than traditional products. This technical achievement was made public on November 6th at the 2018 IEEE Asian Solid State Circuits Conference (A-SSCC 2018) in Taiwan.

Deep learning calculations usually require a large number of multiply-accumulate (MAC) operations, which leads to problems such as long calculation time and high energy consumption. Although a series of techniques have been proposed to reduce the number of bits representing parameter (bit precision) to reduce the total amount of computation, and one of the algorithms can reduce the bit precision to one or two bits, these techniques also bring identification The problem of reduced accuracy. The new algorithm developed by Toshiba Memory Co., Ltd. optimizes the bit precision of each filter [2] MAC operation in each layer of neural network and reduces MAC operations. Using the new algorithm can reduce MAC operations and reduce the degradation of recognition accuracy.

In addition, Toshiba Memory Co., Ltd. has successfully developed a new hardware architecture called bit parallel method, which is suitable for MAC operations with different bit precision. The method divides various bit precisions into one bit one by one and can perform 1-bit operations in parallel in a myriad of MAC units. Compared with the traditional MAC architecture that performs serial operations, this method can significantly improve the utilization efficiency of the MAC unit.

Toshiba Memory Co., Ltd. implemented a deep neural network on the FPGA using various bit precision and bit parallel MAC architectures - ResNet50 [3]. Taking image recognition of ImageNet[4] image dataset as an example, thanks to the support of the above technology, the operation time and energy consumption of identifying image data are reduced to 25%, and the recognition accuracy is reduced compared with the traditional method. Reduced.

Artificial intelligence (AI) is expected to be implemented in a variety of devices. The high-speed, low-power technology developed for deep learning processors is expected to be applied to a variety of edge devices such as smartphones and HMDs [5] and data centers that require low power consumption. High-performance processors such as GPUs are important devices for artificial intelligence to achieve high-speed computing. Memory and memory are also one of the most important devices for artificial intelligence, and they will inevitably need to use big data. Toshiba Memory Co., Ltd. will continue to focus on the development of artificial intelligence technology, while promoting innovation in memory and memory to lead data-oriented computing.

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